LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY KeyRecver IS
	PORT
	(
		Clk : IN std_logic;
		Reset : IN std_logic;
		Enable : IN std_logic;
		Rxd_RecvData : IN std_logic_vector(7 DOWNTO 0);
		RecvAvail : IN std_logic;
		P2KeyState : OUT std_logic_vector(5 DOWNTO 0)
	);
END ENTITY;

ARCHITECTURE rtl OF KeyRecver IS
	TYPE State_Type IS (Idle, Init, Sending, Sending_Wait);
	SIGNAL state : State_Type;
	SIGNAL DataCache : std_logic_vector(7 DOWNTO 0);
BEGIN
	DataCache <= Rxd_RecvData;
	
	cMainCtl : PROCESS(Clk, Reset)
	BEGIN
		IF Reset = '0' THEN
			state <= Idle;
		ELSIF rising_edge(Clk) THEN
			IF Enable = '1' AND RecvAvail = '1' THEN
--				IF DataCache(7 DOWNTO 6) = "00" THEN
					P2KeyState <= DataCache(5 DOWNTO 0);
--				END IF;
			END IF;
		END IF;
	END PROCESS;
END rtl;
